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? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80d481d3 asynccellularram_16_32.fm - rev. a 2/18/04 en 1 ?2004 micron technology, inc. all rights reserved. 2 meg x 16, 1 meg x 16 async/page cellularram memory advance ? asynchronous cellularram tm mt45w2mw16pafa mt45w1mw16pafa mt45w2ml16pafa mt45w1ml16pafa features ? asynchronous and page mode interface random access time: 70ns, 85ns page mode read access sixteen-word page size interpage read access: 70ns, 85ns intrapage read access: 20ns, 25ns v cc , v cc q voltages 1.70v?1.95v v cc 1.70v?2.25v v cc q (option w) 2.30v?2.70v v cc q (option v?contact factory) 2.70v?3.30v v cc q (option l) low power consumption asynchronous read < 25ma intrapage read < 15ma standby: 110a (32mb?standard), 70a (16mb) 90a (32mb?low-power option) deep power-down < 10a low-power features temperature compensated refresh (tcr) on-chip sensor control partial array refresh (par) deep power-down (dpd) mode figure 1: 48-ball fbga note: see table 1 on page 3 for ball descriptions. see figure 21 on page 24 for the 48-ball mechanical drawing. part number example: mt45w2ml16pafa-70lwt options designator configuration 2 meg x 16 mt45w2mx16pa 1 meg x 16 mt45w1mx16pa vcc core voltage supply 1.8v ? mt45wxmx16pa w vccq i/o voltage 3.0v ? mt45wxml16pa l 2.5v ? mt45wxmv16pa v 1 1.8v ? mt45wxmw16pa w package 48-ball fbga fa 48-ball fbga?lead-free ba 1 access time 60ns -60 1 70ns -70 85ns -85 options (continued) designator standby power standard none low-power (32mb) l operating temperature range wireless (-25c to +85c) wt industrial (-40c to +85c) it 1 note 1: contact factory. a b c d e f g h 1 2 3 4 5 6 top view (bump down) lb# dq8 dq9 v ss q v cc q dq14 dq15 a18 oe# ub# dq10 dq11 dq12 dq13 a19 a8 a0 a3 a5 a17 nc a14 a12 a9 a2 ce# dq1 dq3 dq4 dq5 we# a11 zz# dq0 dq2 v cc v ss dq6 dq7 a20 a1 a4 a6 a7 a16 a15 a13 a10
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 2 ?2004 micron technology, inc. all rights reserved. general description micron ? cellularram ? products are high-speed, cmos dynamic random access memories that have been developed for low-powe r portable applications. the mt45w2mx16pa is a 32mb device organized as 2 meg x 16 bits, and the mt45w1mx16pa is a 16mb device organized as 1 meg x 16 bits. these devices include the industry-standard, asynchronous memory interface found on other low-power sram or pseudo sram offerings. operating voltages have been reduced in an effort to minimize power consumption. the core voltage has been reduced to a 1.80v operating level. to maintain compatibility with different memory bus interfaces, cellularram devices are avai lable with i/o voltages of 3.00v, 2.50v or 1.80v. a user-accessible configuration register (cr) defines how the cellularram device performs on-chip refresh and whether page mode read accesses are permitted. this register is automatically loaded with a default set- ting during power-up and can be updated at any time during normal operation. to operate seamlessly on an asynchronous memory bus, cellularram products incorporate a transparent self refresh mechanism. the hidden refresh requires no additional support from the system memory con- troller and has no significan t impact on device read/ write performance. special attention has been focused on current con- sumption during self refresh. cellularram products include three system-accessible mechanisms to mini- mize refresh current. temperature compensated refresh (tcr) uses an on-chip sensor to adjust the refresh rate to match the device temperature. the refresh rate decreases at lower temperatures to mini- mize current consumption during standby. tcr can also be set by the system for maximum device temper- atures of +85c, +45c, and +15c. setting the sleep enable pin zz# to low enables one of two low-power modes: partial array refresh (par); or deep power- down (dpd). par limits refresh to only that part of the dram array that contains essential data. dpd halts refresh operation altogether and is used when no vital information is stored in the device. these three refresh mechanisms are accessed through the cr. figure 2: functional block diagram 2 meg x 16 and 1 meg x 16 note: functional block diagrams il lustrate simplified device operation. see truth table, pin descriptions, and timing diagrams for detailed information. a[20:0] (for 32mb) a[19:0] (for 16mb) input/ output mux and buffers control logic 2,048k x 16 (1,024k x 16) dram memory array dq[7:0] dq[15:8] address decode logic lb# ub# ce# we# oe# zz# configuration register (cr)
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 3 ?2004 micron technology, inc. all rights reserved. note: 1. when lb# and ub# are in select mode (low), dq[15:0] are affected. when lb# only is in select mode, only dq[7:0] are affected. when ub# only is in th e select mode, dq[15:8] are affected. 2. when the device is in standby mode, control inputs (w e#, oe#), address inputs, and data inputs/outputs are inter- nally isolated from an y external influence. 3. when we# is invoked, the oe# in put is internally di sabled and has no effect on the i/os. 4. the device will cons ume active power in this mode whenever addresses are changed. 5. v in = v cc q or 0v; all device balls must be static (unswitche d) in order to achieve minimum standby current. 6. dpd is enabled when configur ation register bit cr[4] is ?0?; otherwise, par is enabled. table 1: fbga ball descriptions fbga ball assignment symbol type description a3, a4, a5, b3, b4, c3, c4, d4, h2, h3, h4, h5, g3, g4, f3, f4, e4, d3, h1, g2, h6 a[20:0] input address inputs: inputs for the address acce ssed during read or write operations. the address lines are also used to define the value to be load ed into the cr. on the 16mb device, a20 (ball h6) is not internally connected. a6 zz# input sleep enable: when zz# is low, the cr ca n be loaded or the device can enter one of two low-power modes (dpd or par). b5 ce# input chip enable: activates the device when low. when ce# is high, the device is disabled and goes into standby power mode. a2 oe# input output enable: enables the output buffers when low. when oe# is high, the output buffers are disabled. g5 we# input write enable: enables write operations when low. a1 lb# input lower byte enable. dq[7:0] b2 ub# input upper byte enable. dq[15:8] b6, c5, c6, d5, e5, f5, f6, g6, b1, c1, c2, d2, e2, f2, f1, g1 dq[15:0] input/ output data inputs/outputs. e3 nc ? not internally connected. d6 v cc supply device power supply: (1.7v?1.95v) powe r supply for device core operation. e1 v cc q supply i/o power supply: (1.8v, 2.5v, 3.0v) power supply for input/output buffers. e6 v ss supply v ss must be connected to ground. d1 v ss q supply v ss q must be connected to ground. table 2: bus operations mode power ce# we# oe# lb#/ub# zz# dq[15:0] 1 notes standby standby h x x x h high-z 2, 5 read active l h l l h data-out 1, 4 write active l l x l h data-in 1, 3, 4 no operation idle l x x x h x 4, 5 par partial array refresh h x x x l high-z 6 dpd deep power-down h x x x l high-z 6 load configuration register active l l x x l high-z
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 4 ?2004 micron technology, inc. all rights reserved. table 3: abbreviated component marks? cellularram fbga-packaged components part number engineering sample qualified product mt45w2mw16pafa-85 wt px400 pw400 mt45w2mw16pafa-70 wt px401 pw401 mt45w2ml16pafa-85 wt px403 pw403 mt45w2ml16pafa-70 wt px404 pw404 mt45w1mw16pafa-85 wt px104 pw104 mt45w1mw16pafa-70 wt px105 pw105 mt45w1ml16pafa-85 wt px107 pw107 mt45w1ml16pafa-70 wt px108 pw108
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 5 ?2004 micron technology, inc. all rights reserved. functional description in general, the mt45w2mx16pa device and the mt45w1mx16pa device are high-density alternatives to sram and pseudo sram products, popular in low- power, portable applications. the mt45w2mx16pa contains 33,554,432 bits organized as 2,097,152 addresses by 16 bits.the mt45w1mx16pa contains 16,777,216 bits organized as 1,048,576 addresses by 16 bits. these devices include the industry-standard, asyn- chronous memory interface found on other low-power sram or pseudo sram offerings. page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. power-up initialization cellularram products incl ude an on-chip voltage sensor that is used to laun ch the power-up initializa- tion process. initialization will load the cr with its default setting. v cc and v cc q must be applied simul- taneously, and when they reach a stable level above 1.70v, the device will require 150s to complete its self- initialization process (see figure 3 below). during the initialization period, ce# should remain high. when initialization is complete, the device is ready for nor- mal operation. figure 3: power-up initialization timing bus operating modes the mt45w2mx16pa and the mt45w1mx16pa cellularram products incorporate the industry-stan- dard, asynchronous interface found on other low- power sram or pseudo sram offerings. this bus interface supports asynchronous read and write operations as well as the bandwidth-enhancing page mode read operation. the specific interface that is supported is defined by the value loaded into the cr. asynchronous mode cellularram products power up in the asynchro- nous operating mode. this mode uses the industry- standard sram control interface (ce#, oe#, we#, lb#/ ub#). read operations (figure 4) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations (figure 5) occu r when ce#, we#, and lb#/ ub# are driven low. during write operations, the level of oe# is a ?don't care?; we# will override oe#. the data to be written will be latched on the rising edge of ce#, we#, or lb#/ub# (whichever occurs first). figure 4: read operation figure 5: write operation vcc vccq device initialization vcc = 1.7v device ready for normal operation t pu > 150s address valid data ce# don?t care data valid oe# we# lb#/ub# t rc = read cycle time address address valid data ce# don?t care data valid oe# we# lb#/ub# t wc = write cycle time address
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 6 ?2004 micron technology, inc. all rights reserved. page mode read operation page mode is a performance-enhancing extension to the legacy asynchronous read operation. in page- mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be quickly read by simply changing the low-order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. addresses a[4] and higher must remain fixed during the entire page mode access. figure 6 shows the timing diagram for a page mode access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. write op erations do not include comparable page mode functionality. figure 6: page read operation lb#/ub# operation the lower byte (lb#) enable and upper byte (ub#) enable signals allow for byte-wide data transfers. dur- ing read operations, enabled bytes are driven onto the dqs. the dqs associated with a disabled byte are put into a high-z state during a read operation. dur- ing write operations, any disabled bytes will not be transferred to the memory array and the internal value will remain unchanged. during a write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (high) during an operation, the device will disable the data bus from receiving or transmitting data. although the device will seem to be deselected, the device remains in an active mode as long as ce# remains low. low power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation on the full array. standby operation occurs when ce# and zz# are high. the device will enter a reduced power state during read and write operations where the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. temperature compensated refresh temperature compensated refresh (tcr) allows for adequate refresh at different temperatures. this cellularram device includes an on-chip temperature sensor. when the sensor is enabled, it continually adjusts the refresh rate according to the operating temperature. the on-chip sensor is enabled by default. three fixed refresh rates are also available, corre- sponding to temperature thresholds of +15c, +45c, and +85c. the setting select ed must be for a tempera- ture higher than the case temperature of the cellular- ram device. if the case temperature is +35c, the system can minimize self-refresh current consump- tion by selecting the +45 c setting. the +15c setting would result in inadequate refreshing and cause data corruption. partial array refresh partial array refresh (par) restricts refresh operation to a portion of the total memory array. this feature enables the system to reduce refresh current by only refreshing that part of the memory array that is abso- lutely necessary. the refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. data stored in addresses not receiving refresh will become corrupted. the mapping of these partitions can start at either the beginning or the end of the address map (tables 5 and 6 on page 11). read and write operations are ignored during par operation. the device only enters par mode if the sleep bit in the cr has been set high (cr[4] = 1). par can be initi- ated by bring the zz# pin to the low state for longer than 10s. returning zz# to high will cause an exit from par and the entire ar ray will be immediately available for read and write operations. alternatively, par can be initiated using the cr soft- ware access sequence (see software access to the con- figuration register on page 8). par is enabled data ce# don?t care oe# we# lb#/ub# address add[0] add[1] add[2] add[3] d[1] d[2] d[3] t aa t apa t apa t apa d[0]
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 7 ?2004 micron technology, inc. all rights reserved. immediately upon setting cr[4] to ?1? using this method. however, using software access to write to the cr alters the function of the zz# pin so that zz# low no longer initiates par, although zz# continues to enable writes to the cr. this functional change per- sists until the next time the device is powered up. (see figure 7.) deep power-down operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used when the system does not require the storage provided by the cellularram device. any stored data will become cor- rupted when dpd is entered. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initia lization procedure before normal operations can resume. read and write operations are ignored during dpd operation. the device can only enter dpd if the sleep bit in the cr has been set low (cr[4] = 0). dpd is initiated by bringing the zz# pin to the low state for longer than 10s. returning zz# to high will cause the device to exit dpd and begin a 150s initialization pro- cess. during this 150s period, the current consump- tion will be higher than the specified standby levels but considerably lower than the active current specifica- tion. driving the zz# pin low will place the device in the par mode if the sleep bit in the cr has been set high (cr[4] = 1). the device should not be put into dpd using cr software access. figure 7: software access par functionality no yes power-up to enable par, bring zz# low for 10s. change to zz# functionality. par permanently enabled, independent of zz# level. software load executed?
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 8 ?2004 micron technology, inc. all rights reserved. configuration register operation the configuration register (cr) defines how the cel- lularram device performs its transparent self refresh. altering the refresh para meters can dramatically reduce current consumption during standby mode. page mode control is also embedded into the cr. this register can be updated anytime while the device is operating in a standby state. table 4 on page 11 describes the control bits used in the cr. at power up, the cr is set to 0010h. access using zz# the cr can be loaded using a write operation immediately after zz# makes a high-to-low transi- tion (figure 8). the values placed on addresses a[20:0] are latched into the cr on the rising edge of ce# or we#, whichever occurs fi rst. lb#/ub# are ?don?t care.? access using zz# is write only. figure 8: load configuration register operation software access to the configuration register the contents of the cr can either be read or modi- fied using a software sequence. the nature of this access mechanism may eliminate the need for the zz# pin. if the software mechanism is used, the zz# pin can simply be tied to v cc q. the port line typically used for zz# control purposes will no longer be required. how- ever, zz# should not be tied to v cc q if the system will use dpd; dpd cannot be enabled or disabled using the software access sequence. the cr is loaded using a four-step sequence con- sisting of two read operations followed by two write operations (see figure 8). the read sequence is virtu- ally identical except that an asynchronous read is performed during the fourth operation (see figure 9 on page 9). the address used during all read and write oper- ations is the highest address of the cellularram device being accessed (1fffffh for 32mb and fffffh for 16mb); the contents of this address are not changed by using this sequence. the data bus is used to transfer data into or out of the cr. writing to the cr using the software sequence mod- ifies the function of the zz# pin. once the software sequence loads the cr, the level of the zz# pin no longer enables par operation. par operation will be updated whenever the software sequence loads a new value into the cr. this zz# functionality will continue until the next time the devi ce is powered-up. the oper- ation of the zz# pin is not affected if the software sequence is only used to read the contents of the cr. the use of the software sequence does not affect the ability to perform the standard (zz# controlled) method of loading the cr. address valid ce# zz# we# t < 500ns address
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 9 ?2004 micron technology, inc. all rights reserved. figure 9: software access lo ad configuration register figure 10: software access r ead configuration register note: ce# must be high for 150ns before performing the cycle that reads the configuration register. address (max) address (max) address (max) address (max) xxxxh xxxxh 0000h cr value in address ce# oe# we# lb#/ub# data don't care read read write write address (max) address (max) address (max) address (max) xxxxh xxxxh 0000h cr value out a ddress ce# oe# we# lb#/ub# data don't care read read write read note
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 10 ?2004 micron technology, inc. all rights reserved. partial array refresh (cr[2:0]) default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the sys- tem to reduce current by only refreshing that part of the memory array required by the host system. the refresh options are full array, three-quarters array, one- half array, one-quarter array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see tables 5 and 6 on page 11). sleep mode (cr[4]) default = par enabled, dpd disabled the sleep mode bit determines which low-power mode is to be entered when zz# is driven low. if cr[4] = 1, par operation is enabled. if cr[4] = 0, dpd opera- tion is enabled. par can also be enabled directly by writing to the cr using the software access sequence. note that this then disables zz# initiation of par. dpd cannot be enabled or disabled using the software access sequence; this should only be done using zz# to access the cr. dpd operation disables all refresh-related activity. this mode will be used when the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re- enabled, the cellularram device will require 150s to perform an initialization procedure before normal operation can resume. dpd should not be enabled using cr software access. temperature compensated refresh (cr[6:5]) default = on-chip temperature sensor this cellularram device includes an on-chip tem- perature sensor that automa tically adjusts the refresh rate according to the operating temperature. the on- chip tcr is enabled by clearing both of the tcr bits in the refresh configuration register (cr[6:5] = 00b). any other tcr setting enables a fixed refresh rate. when the on-chip temperature sensor is enabled, the device continually adjusts the refresh rate according to the operating temperature. the tcr bits also allow for adequate fixed-rate refresh at three different temperature thresholds (+15c, +45c, and +85c). the setting selected must be for a temperature higher than the case tempera- ture of the cellularram device. if the case tempera- ture is +35c, the system can minimize self refresh current consumption by se lecting the +45c setting. the +15c setting would result in inadequate refreshing and cause data corruption. page mode read operation (cr[7]) default = disabled the page mode operation bit determines whether page mode read operations are enabled. in the power-up default state, page mode is disabled.
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 11 ?2004 micron technology, inc. all rights reserved. table 4: configuration register bit mapping par a4 a3 a2 a1 a0 configuration register address bus 4 1 2 3 0 reserved 6 5 a5 0 1 sleep mode dpd enabled par enabled (default) cr[4] tcr cr[6] cr[5] 11 1 1 00 0 0 maximum case temp. +85?c internal sensor (default) +45?c +15?c a6 20? 8 reserved a[20:8] cr[1] 0 0 1 1 cr[0] 0 1 0 1 par refresh coverage full array (default) bottom 3/4 array bottom 1/2 array bottom 1/4 array cr[2] 0 0 0 0 00 1 01 1 1 0 1 11 1 none of array top 3/4 array top 1/2 array top 1/4 array sleep must be set to "0" all must be set to "0" a7 7 page 0 1 page mode enable/disable page mode disabled (default) page mode enabled cr[7] table 5: 32mb address patterns for par (cr[4] = 1) cr[2] cr[1] cr[0] active section address space size density 0 0 0 full die 000000h?1 fffffh 2 meg x 16 32mb 0 0 1 three-quarters of die 00 0000h?2fffffh 1.5 meg x 16 24mb 0 1 0 one-half of die 00000 0h?1fffffh 1 meg x 16 16mb 0 1 1 one-quarter of die 00 0000h?0fffffh 512k x 16 8mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 three-quarters of die 10 0000h?3fffffh 1.5 meg x 16 24mb 1 1 0 one-half of die 20000 0h?3fffffh 1 meg x 16 16mb 1 1 1 one-quarter of die 30 0000h?3fffffh 512k x 16 8mb table 6: 16mb address patterns for par (cr[4] = 1) cr[2] cr[1] cr[0] active section address space size density 0 0 0 full die 00000h?fffffh 1 meg x 16 16mb 0 0 1 three-quarters of di e 00000h?bffffh 768k x 16 12mb 0 1 0 one-half of die 00000h?7ffffh 512k x 16 8mb 0 1 1 one-quarter of die 00000h?3ffffh 256k x 16 4mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 three-quarters of die 40000h?fffffh 768k x 16 12mb 1 1 0 one-half of die 80000h?fffffh 512k x 16 8mb 1 1 1 one-quarter of die c0000h?fffffh 256k x 16 4mb
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 12 ?2004 micron technology, inc. all rights reserved. absolute maximum ratings* voltage to any ball except v cc , v cc q relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50v to (4.0v or vccq + 0.3v, whichever is less) voltage on v cc supply relative to v ss . . -0.20v to 2.45v voltage on v cc q supply relative to v ss . -0.20v to 4.0v storage temperature . . . . . . . . . . . . . . . . -55 c to 150 c operating temperature (case) wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . -25 c to 85 c industrial . . . . . . . . . . . . . . . . . . . . . . . . . -40 c to 85 c soldering temperature and time 10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 c *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. note: 1. input signals may over shoot to vccq + 1.0v for periods less than 2ns duri ng transitions. 2. input signals ma y undershoot to vss - 1.0v for peri ods less than 2ns during transitions 3. this parameter is specified with the outputs disabl ed to avoid external loading ef fects. the user must add the cur- rent required to drive output capacita nce expected in the actual system. 4. i sb (max) values measured with par set to full array and tcr set to +85c. in order to achieve low standby cur- rent, all inputs must be driven to v cc q or v ss . table 7: electrical characteri stics and operating conditions wireless temperature (-25oc t c +85 oc) industrial temperature (-40oc < t c < +85oc) description conditions symbol min max units notes supply voltage v cc 1.70 1.95 v i/o supply voltage v cc q l: 3.00v 2.70 3.30 v v: 2.50v 2.30 2.70 v w:1.80v 1.70 2.25 v input high voltage v ih 1.4 v cc q + 0.2 v 1 input low voltage v il -0.2 +0.4 v 2 output high voltage i oh = -0.2ma v oh 0.80 v cc qv output low voltage i ol = 0.2ma v ol 0.20 v cc qv input leakage current v in = 0 to v cc qi li 1 a output leakage current oe# = v ih or chip disabled i lo 1 a operating current asynchronous random read v in = v cc q or 0v chip enabled, i out = 0 i cc 1 -70 25 ma 3 -85 20 asynchronous page read v in = v cc q or 0v chip enabled, i out = 0 -70 15 -85 12 write operating current v in = v cc q or 0v chip enabled i cc 2 -70 25 ma -85 20 standby current v in = v cc q or 0v ce# = v cc q i sb 32mb?std 110 a4 32mb?l 90 16mb 70
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 13 ?2004 micron technology, inc. all rights reserved. note: i tcr (max) values measured with full array refresh. note: i par (max) values measured with tcr set to 85c. table 8: temperature compensated re fresh specifications and conditions description conditions symbol power max case temperature setting (cr[6:5]) max units temperature compensated refresh standby current v in = v cc q or 0v, ce# = v cc q i tcr 32mb standard (no desig.) +85c 110 a +45c tbd a +15c tbd a 32mb low-power option (l) +85c 90 a +45c tbd a +15c tbd a 16mb +85c 70 a +45c tbd a +15c tbd a table 9: partial array refresh specifications and conditions description conditions symbol power array partition max units partial array refresh current v in = v cc q or 0v zz# = 0v cr[4] = 1 i par 32mb standard (no desig.) full 110 a 3/4 tbd a 1/2 tbd a 1/4 tbd a 0 tbd a 32mb low-power option (l) full 90 a 3/4 tbd a 1/2 tbd a 1/4 tbd a 0 tbd a 16mb full 70 a 3/4 tbd a 1/2 tbd a 1/4 tbd a 0 tbd a table 10: deep power-down sp ecifications and conditions description conditions symbol typ units deep power-down v in = v cc q or 0v; +25c zz# = 0v cr[4] = 0 i zz 10 a
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 14 ?2004 micron technology, inc. all rights reserved. note: 1. these parameters are verified in device characterization and are not 100% tested. figure 11: ac input/outp ut reference waveform note: 1. ac test inputs are driven at v cc q for a logic 1 and v ss for a logic 0. input rise and fall times (10% to 90%) < 1.6ns. 2. input timing begins at v cc /2. due to the possibility of a difference between v cc and v cc q, the input test point may not be shown to scale. 3. output timing ends at v cc q/2. figure 12: output load circuit table 11: capacitance specifications and conditions description conditions symbol min max units notes input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in ?6pf1 input/output capacitance (dq) c io ?6pf1 output test points input 1 v cc q v ss v cc q/2 3 v cc /2 2 dut vccq r1 r2 30pf test point table 12: output load circuit v cc q r1/r2 1.8v 2.7k ? 2.5v 3.7k ? 3.0v 4.5k ?
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 15 ?2004 micron technology, inc. all rights reserved. note: 1. high-z to low-z timings are tested wi th the circuit shown in figure 12 on page 14. the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 2. low-z to high-z timings are tested wi th the circuit shown in figure 12 on page 14. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. table 13: read cycle timing requirements parameter symbol -70 -85 units notes min max min max address access time t aa 70 85 ns page access time t apa 20 25 ns lb#/ub# access time t ba 70 85 ns lb#/ub# disable to high-z output t bhz 88ns2 lb#/ub# enable to low-z output t blz 10 10 ns 1 chip select access time t co 70 85 ns chip disable to high-z output t hz 88ns2 chip enable to low-z output t lz 10 10 ns 1 output enable to valid output t oe 20 20 ns output hold from address change t oh 55ns output disable to high-z output t ohz 88ns2 output enable to low-z output t olz 55ns1 page cycle time t pc 20 25 ns read cycle time t rc 70 85 ns table 14: write cycle timing requirements parameter symbol -70 -85 units notes min max min max address setup time t as 00ns address valid to end of write t aw 70 85 ns byte select to end of write t bw 70 85 ns ce# high time during write t ceh 55ns maximum ce# pulse width t cem 10 10 s chip enable to end of write t cw 70 85 ns data hold from write time t dh 00ns data write setup time t dw 23 25 ns chip enable to low-z output t lz 10 10 ns 1 end write to low-z output t ow 55ns write cycle time t wc 70 85 ns write to high-z output t whz 88ns2 write pulse width t wp 46 50 ns write pulse width high t wph 10 10 ns write recovery time t wr 00ns
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 16 ?2004 micron technology, inc. all rights reserved. timing diagrams figure 13: power-up initialization period table 15: load configuration re gister timing requirements description symbol -70 -85 units notes min max min max address setup time t as 00ns address valid to end of write t aw 70 85 ns chip deselect to zz# low t cdzz 55ns chip enable to end of write t cw 70 85 ns write cycle time t wc 70 85 ns write pulse width t wp 40 40 ns write recovery time t wr 00ns zz# low to we# low t zzwe 10 500 10 500 ns table 16: deep power-down timing requirements description symbol -70 -85 units notes min max min max chip deselect to zz# low t cdzz 55ns deep power-down recovery t r 150 150 s minimum zz# pulse width t zzmin 10 10 s device ready for normal operation vcc, vccq = 1.7v t pu vcc (min) table 17: power-up initializ ation timing requirements parameter symbol -70 -85 units notes min max min max power-up initialization period t pu 150 150 s
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 17 ?2004 micron technology, inc. all rights reserved. figure 14: load con figuration register address zz# t wc t aw t wr t as ce# lb#/ub# t zzwe don?t care we# t wp t cdzz opcode t cw oe# table 18: load configuration re gister timing requirements symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t wc 70 85 ns t aw 70 85 ns t wp 40 40 ns t cdzz 55ns t wr 00ns t cw 70 85 ns t zzwe 1050010500ns
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 18 ?2004 micron technology, inc. all rights reserved. figure 15: deep power-down?entry/exit zz# ce# t zz (min) don?t care t cdzz t r device ready for normal operation table 19: deep power-down timing parameters symbol -70 -85 units min max min max t cdzz 55ns t r 150 150 s t zz (min) 10 10 s
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 19 ?2004 micron technology, inc. all rights reserved. figure 16: single re ad operation (we# = v ih ) address oe# t rc t aa data-out ce# lb#/ub# t olz t lz don?t care undefined high-z high-z data valid t ohz t ba t bhz t hz t blz t co t oe address valid table 20: read timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t ba 70 85 ns t oe 20 20 ns t bhz 88ns t ohz 88ns t blz 10 10 ns t olz 55ns t co 70 85 ns t rc 70 85 ns t hz 88ns
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 20 ?2004 micron technology, inc. all rights reserved. figure 17: page mode read operation (we# = v ih ) address a[20:4] oe# t aa data-out ce# lb#/ub# t olz t lz don?t care undefined high-z high-z data valid data valid data valid data valid t ohz t ba t bhz t hz t cem t blz t co address a[3:0] t rc t oh t pc address valid t apa t oe table 21: page mode read timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t apa 20 25 ns t oe 20 20 ns t ba 70 85 ns t oh 55ns t bhz 88ns t ohz 88ns t blz 10 10 ns t olz 55ns t cem 10 10 s t pc 20 25 ns t co 70 85 ns t rc 70 85 ns t hz 88ns
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 21 ?2004 micron technology, inc. all rights reserved. figure 18: write cycle (we# control) address we# t wc t aw t wr data-in ce# lb#/ub# t bw t whz t ow t dh t dw t as t wp t wph don?t care high-z data-out data valid t cw t cem oe# address valid table 22: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t ow 55ns t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t whz 88ns t cem 10 10 s t wp 46 50 ns t cw 70 85 ns t wph 10 10 ns t dh 00ns t wr 00ns t dw 23 25 ns
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 22 ?2004 micron technology, inc. all rights reserved. figure 19: write cycle (ce# control) address we# t wc t aw t cw t cem t wr t ceh data-in ce# lb#/ub# t bw t whz t lz t as t dh t dw t wp don?t care high-z data-out data valid oe# table 23: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t dw 23 25 ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t ceh 55ns t whz 88ns t cem 10 10 s t wp 46 50 ns t cw 70 85 ns t wr 00ns t dh 00ns
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 23 ?2004 micron technology, inc. all rights reserved. figure 20: write cycle (lb#/ub# control) address we# t wc t aw t wr data-in ce# lb#/ub# t bw t whz t dh t as t dw t lz don?t care data-out data valid t cem t cw oe# high-z table 24: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t dw 23 25 ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cem 10 10 s t whz 88ns t cw 70 85 ns t wr 00ns t dh 00ns
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, and the micron and m logos are trademarks of micron technology, inc. cellularram is a trademark of micron technology, inc. inside the u.s. and a trademark of infineon technologies outside the u.s. all other trademarks are the property of their respective owners. 2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 24 ?2004 micron technology, inc. all rights reserved. figure 21: 48-ball fbga note: 1. all dimensions in millimeters, max/min or typical where noted. 2. package width and length do not in clude mold protrusion; allowable mold protrusion is 0.25mm per side. data sheet designation: advance this data sheet contains initial descriptions of prod- ucts still in development. ball a1 id 1.00 max 4.00 0.05 3.00 0.05 1.875 0.050 6.00 0.10 c l c l solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3% ag, 0.5% cu solder ball pad: ?0.30 solder mask defined mold compound: epoxy novolac substrate: plastic laminate 0.75 typ 0.75 typ 8.00 0.10 5.25 2.625 0.05 ball a1 ball a1 id 3.75 0.70 0.05 seating plane 0.10 c c ball a6 solder ball diameter refers to post reflow condition. the pre-reflow diameter is ?0.35. 48x ?0.35
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 25 ?2004 micron technology, inc. all rights reserved. appendix a how extended timings impact cellularram tm operation introduction cellularram ? products use a dram technology that periodically requires refresh to ensure against data corruption. cellularra m devices include on-chip circuitry that performs the required refresh in a man- ner that is completely transparent in systems with nor- mal bus timings. the refresh circuitry does impose constraints on timings in sy stems that take longer than 10s to complete operations. this appendix describes cellularram timing requirements in systems that per- form extended operations. table 25 below summarizes this information. write operation the timing parameters provided in table 14 on page 15 require that all write operations must be completed within 10s. after completing a write operation, the device must either enter standby (by transitioning ce# high), or else perform a second operation (read or write) using a new address. fig- ures 22 and 23 demonstrate these constraints as they apply during an asynchronous (page-mode-disabled) operation. either the ce# active period ( t cem in figure 22) or the address valid period ( t tm in figure23) must be less than 10s during any write operation, otherwise, the extended write timings must be used. figure 22: extended timing for t cem figure 23: extended timing for t tm ce# address t cem 10s < ce# address < t tm 10 s table 25: extended cycle impact on read and write cycles page mode timing constraint read cycle write cycle disabled t cem and t tm > 10s (see figures 22 and 23 above.) no impact. must use extended write timing. (see figure 24 on page 26.) enabled t cem > 10s (see figure 22 above.) not allowed.
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 26 ?2004 micron technology, inc. all rights reserved. page mode read operation when a cellularram device is configured for page mode operation, the address inputs are used to accel- erate read accesses and cannot be used by the on-chip circuitry to schedule refresh. if ce# is low longer than the t cem maximum time of 10s, or no refresh will occur and data may be lost. page mode should only be used in systems that can limit ce#-low times to less than 10s. extended write timing modified timings are required during extended write operations (see figure 24 below). an extended write operation requires that both the write pulse width ( t wp) and the data valid period ( t dw ) be length- ened to at least the minimum write cycle time ( t wc [min]). these increased timings ensure that time is available for both a refres h operation and a successful completion of the write operation. figure 24: extended write operation data-in address ce# lb#/ub# we# t cem or t tm > 10s t wp t wc (min) > t dw t wc (min) > data valid
2 meg x 16, 1 meg x 16 async/page cellularram memory advance 09005aef80d481d3 micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32.fm - rev. a 2/18/04 en 27 ?2004 micron technology, inc. all rights reserved. revision history rev. a, advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/04 corrected typographic error in software access description. rev. a, advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/04 last address not changed by software access sequence. added on-chip sensor to tcr. clarified software access description. rev. a, advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/03 initial release

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